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W83195AR-WE
200MHZ 3-DIMM CLOCK FOR WHITNEY CHIPSET 1.0 GENERAL DESCRIPTION
The W83195AR-WE is a Clock Synthesizer for Intel Solano chipset. W83195AR-WE provides all clocks required for high-speed RISC or CISC microprocessor and also provides 64 different frequencies of CPU, SDRAM, PCI, 3V66, IOAPIC clocks frequency setting. All clocks are externally selectable with smooth transitions. The W83195AR-WE provides I C serial bus interface to program the registers to enable or disable each clock outputs and provides 0.5% and 0.75% center type spread spectrum to reduce EMI. The W83195AR-WE accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as maintaining 50 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide better than 0.5V /ns slew rate.
2
2.0 PRODUCT FEATURES
* * * * * * * * * * * * 2 CPU clocks 12 SDRAM clocks for 3 DIMMs 8 PCI synchronous clocks. Optional single or mixed supply: (VddR = VddP=VddS = Vdd48 = Vdd3 = 3.3V, VddLAPIC=VddLCPU=2.5V) Skew form CPU to PCI clock -1 to 4 ns, center 2.6 ns Smooth frequency switch with selections from 66.8 to 200 MHz 2 2 I C 2-Wire serial interface and I C read back 0.5% and 0.75% center type spread spectrum Programmable registers to enable/stop each output and select modes (mode as Tri-state or Normal ) Two 48 MHz pins for USB 24 MHz for super I/O 56-pin SSOP package
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Publication Release Date: July 1999 Revision 0.51
W83195AR-WE
PRELIMINARY 3.0 PIN CONFIGURATION
REFX2/*FS3 VddR Xin Xout Vss Vdd3 3V66-0 3V66-1 Vss3 PCICLK0/ *FS0 PCICLK1/ FS1# PCICLK2/*FS2 VssP PCICLK3/ *APIC_SEL PCICLK4 VddP PCICLK5 PCICLK6 PCICLK7 Vss48 48MHz_0 48MHz_1/ FS4# SIO_SEL*/24_48MHz Vdd48 VddS SDRAM 12 SDRAM 11 VssS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VddLAPIC IOAPIC VddLCPU CPUCLK0 CPUCLK1 VssC VddS SDRAM 0 SDRAM 1 SDRAM 2 VssS SDRAM 3 SDRAM 4 SDRAM 5 VddS SDRAM 6 SDRAM 7 SDRAM 8 VssS PD# *SDCLK VddS VssS *SDATA VddS SDRAM 9 SDRAM 10 VssS
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Publication Release Date: July 1999 Revision 0.51
W83195AR-WE
PRELIMINARY 4.0 FREQUENCY SELECTION BY HARDWARE
SSEL4 SSEL3 SSEL2 SSEL1 SSEL0 CPU (MHz) SDRAM (MHz) CPU /SDRAM 3V66 (MHz) PCI(MHz) IOAPIC (MHz) IOAPIC (MHz) APIC_SEL=1 APIC_SEL=0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
83.3 90 75 72 89.07 95.25 121 124 119 114 110 105 66.8 100.2 133.6 133.6 135 125 127 130 140 136 166 155 150 117 107 100.9 145 140 138 137
124.95 90 112.5 108 133.6 95.25 121 124 119 114 110 105 100.2 100.2 133.6 100.2 101.25 125 127 130 140 136 166.00 155 112.5 117 107 100.9 108.75 105 103.5 102.75
2/3 1 2/3 2/3 2/3 1 1 1 1 1 1 1 2/3 1 1 4/3 4/3 1 1 1 1 1 1 1 4/3 1 1 1 4/3 4/3 4/3 4/3
83.30 60.00 75.00 72.00 89.07 63.50 80.67 82.67 79.33 76.00 73.33 70.00 66.80 66.80 66.80 66.80 67.50 83.33 84.67 86.67 70.00 68.00 83.00 77.50 75.00 78.00 71.33 67.27 72.50 70.00 69.00 68.50
41.65 30.00 37.50 36.00 44.53 31.75 40.33 41.33 39.67 38.00 36.67 35.00 33.40 33.40 33.40 33.40 33.75 41.67 42.33 43.33 35.00 34.00 41.50 38.75 37.50 39.00 35.67 33.63 36.25 35.00 34.50 34.25
20.83 15.00 18.75 18.00 22.27 15.88 20.17 20.67 19.83 19.00 18.33 17.50 16.70 16.70 16.70 16.70 16.88 20.83 21.17 21.67 17.50 17.00 20.75 19.38 18.75 19.50 17.83 16.82 18.13 17.50 17.25 17.13
41.65 30.00 37.50 36.00 44.53 31.75 40.33 41.33 39.67 38.00 36.67 35.00 33.40 33.40 33.40 33.40 33.75 41.67 42.33 43.33 35.00 34.00 41.50 38.75 37.50 39.00 35.67 33.63 36.25 35.00 34.50 34.25
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Publication Release Date: July 1999 Revision 0.51
W83195AR-WE
PRELIMINARY 5.0 SERIAL CONTROL 0REGISTERS
The Pin column lists the affected pin number and the @PowerUp column gives the state at true power up. Registers are set to the values shown only on true power up. "Command Code" byte and "Byte Count" byte must be sent following the acknowledge of the Address Byte. Although the data (bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge. After that, the below described sequence (Register 0, Register 1, Register 2, ....) will be valid and acknowledged.
Frequency Table Setting by I2C (SEL5 ~ SEL0)
SSE L5 SS EL4 SS EL3 SS EL2 SS EL1 SS EL0 CPU (MHz) SDRAM (MHz) CPU/S DRAM 3V66 (MHz) PCI(M Hz) IOAPIC (MHz) APIC_SEL=1 IOAPIC (MHz) APIC_SEL=0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
83.3 90 75 72 89.07 95.25 121 124 119 114 110 105 66.8 100.2 133.6 133.6 135 125 127 130 140 136 166 155 150 117 107 100.9 145 140 138
124.95 90 112.5 108 133.6 95.25 121 124 119 114 110 105 100.2 100.2 133.6 100.2 101.25 125 127 130 140 136 166.00 155 112.5 117 107 100.9 108.75 105 103.5
2/3 1 2/3 2/3 2/3 1 1 1 1 1 1 1 2/3 1 1 4/3 4/3 1 1 1 1 1 1 1 4/3 1 1 1 4/3 4/3 4/3
83.30 60.00 75.00 72.00 89.07 63.50 80.67 82.67 79.33 76.00 73.33 70.00 66.80 66.80 66.80 66.80 67.50 83.33 84.67 86.67 70.00 68.00 83.00 77.50 75.00 78.00 71.33 67.27 72.50 70.00 69.00
41.65 30.00 37.50 36.00 44.53 31.75 40.33 41.33 39.67 38.00 36.67 35.00 33.40 33.40 33.40 33.40 33.75 41.67 42.33 43.33 35.00 34.00 41.50 38.75 37.50 39.00 35.67 33.63 36.25 35.00 34.50
20.83 15.00 18.75 18.00 22.27 15.88 20.17 20.67 19.83 19.00 18.33 17.50 16.70 16.70 16.70 16.70 16.88 20.83 21.17 21.67 17.50 17.00 20.75 19.38 18.75 19.50 17.83 16.82 18.13 17.50 17.25
41.65 30.00 37.50 36.00 44.53 31.75 40.33 41.33 39.67 38.00 36.67 35.00 33.40 33.40 33.40 33.40 33.75 41.67 42.33 43.33 35.00 34.00 41.50 38.75 37.50 39.00 35.67 33.63 36.25 35.00 34.50
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Publication Release Date: July 1999 Revision 0.51
W83195AR-WE
PRELIMINARY
0 1 1 1 1 1 137 102.75 4/3 68.50 34.25 17.13 34.25
SSE L5
SS EL4
SS EL3
SS EL2
SS EL1
SS EL0
CPU (MHz)
SDRAM (MHz)
CPU/S DRAM
3V66 (MHz)
PCI(M Hz)
IOAPIC (MHz) APIC_SEL=1
IOAPIC (MHz) APIC_SEL=0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
136 138 139 141 142 142 143 143 144 144 146 146 147 147 148 148 149 152 153 156 157 158 159 160 162 164 170 175 180 185 190
102.00 138.00 104.25 141.00 142.00 106.50 143.00 107.25 144.00 108.00 146 109.50 147 110.25 148.00 111.00 111.75 152.00 114.75 156.00 117.75 158.00 119.25 160.00 121.5 164.00 170.00 175 90 92.5 126.67
4/3 1 4/3 1 1 4/3 1 4/3 1 4/3 1 4/3 1 4/3 1 4/3 4/3 1 4/3 1 4/3 1 4/3 1 4/3 1 1 1 4/3 2 3/2
68.00 69.00 69.50 70.50 71.00 71.00 71.50 71.50 72.00 72.00 73.00 73.00 73.50 73.50 74.00 74.00 74.50 76.00 76.50 78.00 78.50 79.00 79.50 80.00 81.00 82.00 85.00 87.5 60 61.67 63.33
34.00 34.50 34.75 35.25 35.50 35.50 35.75 35.75 36.00 36.00 36.50 36.50 36.75 36.75 37.00 37.00 37.25 38.00 38.25 39.00 39.25 39.50 39.75 40.00 40.50 41.00 42.50 43.75 30 30.83 31.67
17.00 17.25 17.38 17.63 17.75 17.75 17.88 17.88 18.00 18.00 18.25 18.25 18.38 18.38 18.50 18.50 18.63 19.00 19.13 19.50 19.63 19.75 19.88 20.00 20.25 20.50 21.25 21.88 15 15.42 15.83
34.00 34.50 34.75 35.25 35.50 35.50 35.75 35.75 36.00 36.00 36.50 36.50 36.75 36.75 37.00 37.00 37.25 38.00 38.25 39.00 39.25 39.50 39.75 40.00 40.50 41.00 42.50 43.75 30 30.83 31.67
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Publication Release Date: July 1999 Revision 0.51
W83195AR-WE
PRELIMINARY
1 1 1 1 1 1 200.4 133.60 3/2 66.80 33.40 16.70 33.40
5.1 Register 0: Control Register
Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 1 1 1 1 1 1 Pin 26 1 27 30 31 23 21,22 39 REF2X(Active / Inactive) SDRAM11(Active / Inactive) SDRAM10(Active / Inactive) SDRAM9(Active / Inactive) 24/48MHz(Active / Inactive) 48MHz_0, 48MHz_1(Active / Inactive) SDRAM8(Active / Inactive) Description SDRAM12(Active / Inactive)
5.2 Register 1 : SDRAM Register (1 = Active, 0 = Inactive)
Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 1 1 1 1 1 1 Pin 40 41 43 44 45 47 48 49 SDRAM7 (Active / Inactive) SDRAM6 (Active / Inactive) SDRAM5 (Active / Inactive) SDRAM4 (Active / Inactive) SDRAM3 (Active / Inactive) SDRAM2 (Active / Inactive) SDRAM1 (Active / Inactive) SDRAM0 (Active / Inactive) Description
5.3 Register 2: PCI Clock Register (1 = Active, 0 = Inactive)
Bit 7 6 5 4 3 2 @PowerUp 1 1 1 1 1 1 Pin 19 18 17 15 14 13 PCICLK7 (Active / Inactive) PCICLK6 (Active / Inactive) PCICLK5 (Active / Inactive) PCICLK4 (Active / Inactive) PCICLK3 (Active / Inactive) PCICLK2 (Active / Inactive) Description
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Publication Release Date: July 1999 Revision 0.51
W83195AR-WE
PRELIMINARY
1 0 1 1 11 10 PCICLK1 (Active / Inactive) PCICLK0 (Active / Inactive)
5.4 Register 3: CPU Clock Register (1 = Active, 0 = Inactive)
Bit 7 6 5 4 3 2 1 0 @PowerUp X 1 1 X 1 1 1 X Pin 7 8 55 44 43 FS0# 3V66_0(Active / Inactive) 3V66_1(Active / Inactive) FS1# IOAPIC(Active/ Inactive) CPUCLK1 (Active / Inactive) CPUCLK0 (Active / Inactive) FS2# Description
5.5 Register 4: Control Register (1 = Active, 0 = Inactive)
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 0 0 0 0 0 X Pin Description SSEL3 (Frequency table selection by software via I C ) SSEL2 ( Frequency table selection by software via I C) SSEL1 ( Frequency table selection by software via I C) SSEL0 ( Frequency table selection by software via I C) 0 = Selection by hardware 2 1 = Selection by software I C - Bit (1,2, 4:6) 2 SSEL4 (Frequency table selection by software via I C ) SSEL5 (Frequency table selection by software via I C ) APIC_SEL#
2 2 2 2 2
5.6 Register 5: Control Register (1 = Active, 0 = Inactive)
Bit 7 6 5 4 3 @PowerUp 0 1 0 0 X Pin Description 0 = 0.5% Center type Spread Spectrum Modulation 1 = 0.75% Center type Spread Spectrum Modulation SKEW2(SDRAM to CPU Skew programming bit) SKEW1(SDRAM to CPU Skew programming bit) SKEW0(SDRAM to CPU Skew programming bit) FS3#
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Publication Release Date: July 1999 Revision 0.51
W83195AR-WE
PRELIMINARY
2 1 0 X 0 0 FS4# 0 = Normal 1 = Spread Spectrum enabled Reserved
5.7 Register 6: Winbond Chip ID Register (Read Only)
Bit 7 6 5 4 3 2 1 0 @PowerUp 1 0 0 1 1 0 0 0 Pin Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Description
5.8 Register 7: Winbond Chip ID Register (Read Only)
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 1 1 0 0 0 1 Pin Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Version ID Winbond Version ID Winbond Version ID Description
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Publication Release Date: July 1999 Revision 0.51
W83195AR-WE
PRELIMINARY
6.0 ORDERING INFORMATION
Part Number W83195AR-WE Package Type 56 PIN SSOP Production Flow Commercial, 0C to +70C
7.0 HOW TO READ THE TOP MARKING
W83195AR-WE 28051234 814GAB
1st line: Winbond logo and the type number: W83195AR-WE 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 814 G B B 814: packages made in '98, week 14 G: assembly house ID; O means OSE, G means GR A: Internal use code B: IC revision
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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Publication Release Date: July 1999 Revision 0.51
W83195AR-WE
PRELIMINARY 8.0 PACKAGE DRAWING AND DIMENSIONS
.035 .045
DIMENSION IN MM
.045 .055 0.40/0.50 DIA END VIEW
DIMENSION IN INCH
SYMBOL
E
HE
A A1 A2 b c D HE E e L L1 Y
TOP VIEW
SEE DETAIL "A"
c
MIN. NOM MAX. MIN. NOM 0.095 0.101 2.41 2.57 2.79 0.20 0.30 0.41 0.008 0.012 2.34 0.088 0.090 2.24 2.29 0.20 0.25 0.34 0.008 0.010 0.13 0.25 0.005 18.2 18.42 18.54 0.720 0.725 9 10.16 10.31 10.41 0.400 0.406 7.42 0.51 0.61 7.52 0.64 0.81 1.40 7.59 0.76 1.02 0.08 8
MAX. 0.110 0.016 0.092 0.0135 0.010
D
A2
A
Y SEATING PLANE e b
SIDE VIEW A1 PARTING LINE
0.730 0.410 0.292 0.296 0.299 0.020 0.025 0.030 0.024 0.032 0.040 0.055 0.003 0 8
c
0
L L1
DETAIL"A"
Headquarters
No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064
Winbond Electronics (North America) Corp.
2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sale.
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Publication Release Date: July 1999 Revision 0.51

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